corrected links
This commit is contained in:
S. Seegel
parent
204ffdddd4
commit
613f46b479
8 changed files with 679 additions and 8 deletions
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../my-pi-projects/RaspyRFM/connair.py
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72
connair.py
Executable file
72
connair.py
Executable file
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#!/usr/bin/env python2.7
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import socket
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import rfm69
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import sys
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UDP_IP = "0.0.0.0"
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UDP_PORT = 49880
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HELLO_MESSAGE = "HCGW:VC:Seegel Systeme;MC:RaspyRFM;FW:1.00;IP:192.168.2.124;;"
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sock = socket.socket(socket.AF_INET, # Internet
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socket.SOCK_DGRAM) # UDP
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sock.bind((UDP_IP, UDP_PORT))
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#sock.sendto("TXP:0,0,10,20000,350,25,1,3,3,1,1,3,3,1,1,3,3,1,1,3,3,1,1,3,3,1,1,3,3,1,1,3,3,1,1,3,3,1,1,3,3,1,1,3,3,1,1,3,1,3,1,3,3,1,1,17;", ("192.168.178.51", 49880))
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#sys.exit(0)
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rfm = rfm69.Rfm69()
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rfm.SetParams(
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Freq = 433.92,
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TXPower = 13,
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ModulationType = rfm69.OOK,
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SyncPattern = [],
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RssiThresh = -72
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)
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while True:
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data, addr = sock.recvfrom(1024) # buffer size is 1024 bytes
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#data = "TXP:0,0,6,5950,350,25,1,3,3,1,1,3,3,1,1,3,3,1,1,3,3,1,1,3,3,1,1,3,3,1,1,3,3,1,1,3,3,1,1,3,3,1,1,3,3,1,1,3,1,3,1,3,3,1,1,17;"
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#addr = ("123", 5)
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print "received message:", data, "from ", addr
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msg = str(data).split(":")
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if msg[0] == "SEARCH HCGW":
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sock.sendto(HELLO_MESSAGE, addr)
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print "Hello message"
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if msg[0] == "TXP":
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msg[1] = msg[1].replace(";", "")
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cmd = msg[1].split(",")
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rep = int(cmd[2])
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pauselen = int(cmd[3])
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steplen = int(cmd[4])
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numpulse = int(cmd[5])
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pulsedata = cmd[6:]
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pulsedata[numpulse * 2 - 1] = int(pulsedata[numpulse * 2 - 1]) + pauselen / steplen
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bindata = []
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bit = True
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numbit = 0
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bitleft = 0
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for i in range(numpulse * 2):
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for bits in range(int(pulsedata[i])):
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if bitleft == 0:
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bitleft = 8
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bindata.append(0x00)
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bindata[len(bindata) - 1] <<= 1
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if bit:
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bindata[len(bindata) - 1] |= 0x01
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bitleft -= 1
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bit = not bit
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for i in range(bitleft):
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bindata[len(bindata) - 1] <<= 1
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print "bitleft: ", bitleft
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print "reps: ", rep
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print "Pulse data", pulsedata
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print "bin:", bindata
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rfm.SetParams(Datarate = 1000.0 / steplen)
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rfm.SendPacket(bindata * rep)
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../my-pi-projects/RaspyRFM/hamarx.py
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77
hamarx.py
Executable file
77
hamarx.py
Executable file
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#!/usr/bin/env python2.7
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from rfm69 import Rfm69
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import rfm69
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import sys
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import time
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#import types
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#import os
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rfm = Rfm69()
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rfm.SetParams(
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Freq = 433.944,
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Datarate = 4.0, #1 / 250E-06 / 1000,
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Bandwidth = 24000,
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SyncPattern = [0x00, 0x08, 0x00],
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RssiThresh = -80,
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ModulationType = rfm69.OOK
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)
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def staff(byte):
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res = 0
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res |= (byte & 1<<7) >> 4
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res |= (byte & 1<<5) >> 3
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res |= (byte & 1<<3) >> 2
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res |= (byte & 1<<1) >> 1
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return res
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def decode(bindata):
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netdata = [0x00, 0x00, 0x00, 0x00]
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for i in range(0, 64, 2):
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if (bindata[i / 8] >> (i % 8)) & 0x01 == (bindata[i / 8] >> (i % 8 + 1)) & 0x01:
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print "Error", i, hex(bindata[i / 8]), hex(bindata[i / 8] >> (i % 8))
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for i in range(4):
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netdata[i] = staff(bindata[i * 2]) << 4 | staff(bindata[i * 2 + 1])
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print "decode: ",
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for i in range(4):
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print "{0:{fill}2x}".format(netdata[i], fill='0'),
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print ""
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while True:
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data = rfm.ReceivePacket(60)
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zcount = 0
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bindata = []
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binval = 0
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binmask = 0x80
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for d in data:
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rawmask = 0x80
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while (rawmask > 0) and (len(bindata) < 8):
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if (d & rawmask) > 0:
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if zcount == 1:
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binval |= binmask
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binmask >>= 1
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if zcount == 5:
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binmask >>= 1
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if zcount == 11:
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print "Received pause"
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if zcount == 41:
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print "SYNC"
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zcount = 0
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else:
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zcount += 1
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rawmask >>= 1
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if binmask == 0:
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bindata.append(binval)
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binmask = 0x80
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binval = 0
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if len(bindata) == 8:
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decode(bindata)
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break;
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../my-pi-projects/RaspyRFM/intertechno.py
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39
intertechno.py
Executable file
39
intertechno.py
Executable file
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#!/usr/bin/env python2.7
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from rfm69 import Rfm69
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import rfm69
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import sys
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import time
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if len(sys.argv) != 2:
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print "usage: intertechno <CODE>" #12-digit code 12 * ['0' | '1' | 'f']
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print "Example: intertechno 0FF0F0F00FF0"
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sys.exit(1)
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rfm = Rfm69()
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rfm.SetParams(
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Freq = 433.92,
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Datarate = 2.666666,
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TXPower = 13,
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ModulationType = rfm69.OOK,
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SyncPattern = []
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)
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#Frame generation
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def MakeFrame(code, rep):
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data = [0x80, 0x00, 0x00, 0x00] #sync
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b = 0;
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data = []
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for c in code:
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if c == '0':
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data.append(0x88)
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elif c == '1':
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data.append(0xEE)
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elif c == 'F' or c == 'f':
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data.append(0x8E)
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data += [0x80, 0x00, 0x00, 0x00] #sync
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return data * rep
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data = MakeFrame(sys.argv[1], 8)
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rfm.SendPacket(data)
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../my-pi-projects/RaspyRFM/lacrosse.py
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32
lacrosse.py
Executable file
32
lacrosse.py
Executable file
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#!/usr/bin/env python2.7
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from rfm69 import Rfm69
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import rfm69
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import sensors
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from sensors import rawsensor
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import sys
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import time
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rfm = Rfm69()
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rfm.SetParams(
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Freq = 868.300, #MHz center frequency
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Datarate = 9.579, #17.241, #kbit/s baudrate
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ModulationType = rfm69.FSK, #modulation
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SyncPattern = [0x2d, 0xd4], #syncword
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Bandwidth = 200, #kHz bandwidth
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LnaGain = 0x88
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)
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print hex(rfm.ReadReg(0x07))
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print hex(rfm.ReadReg(0x08))
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print hex(rfm.ReadReg(0x09))
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data = []
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while 1:
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data = rfm.ReceivePacket(7)
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obj = rawsensor.CreateSensor(data)
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print(str(obj))
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../my-pi-projects/RaspyRFM/logilightrx.py
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53
logilightrx.py
Executable file
53
logilightrx.py
Executable file
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#!/usr/bin/env python2.7
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from rfm69 import Rfm69
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import rfm69
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import sys
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import time
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#import types
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#import os
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rfm = Rfm69()
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rfm.SetParams(
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Freq = 433.92,
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Datarate = 1 / 275E-06 / 1000,
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Bandwidth = 4000,
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SyncPattern = [0x80, 0x00, 0x00, 0x00],
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RssiThresh = -80,
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ModulationType = rfm69.OOK
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)
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def Decode(bitpos, data):
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frame = 0 #space for decoded logilink frame
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for i in range(bitpos, bitpos + 24 * 4, 4):
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bitpattern = (data[i / 8] << 8) | (data[i / 8 + 1])
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bitpattern <<= i % 8
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bitpattern &= 0xF000
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frame <<= 1
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if bitpattern == 0xe000:
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frame |= 1
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elif bitpattern == 0x8000:
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pass
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else:
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return
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systemcode = frame >> 4
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onoff = (frame >> 3) & 0x01
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ch = frame & 0x07
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return systemcode, onoff, ch
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while True:
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data = rfm.ReceivePacket(60)
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zcount = 0
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binstr = ""
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bitcount = 0
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#print "received raw data:", data[0]
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sync = 0
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for bit in range(len(data[0]) * 8):
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sync <<= 1
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sync |= ((data[0][bit / 8] >> (7 - (bit % 8)))) & 0x01
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sync &= 0xFFFFFFFF
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if sync == 0x80000000: #sync found in frame
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if (bit >= 24 * 4 + 32 - 1): #logilinkframe has 24 bit, 1 logilink-bit = 4 raw-bits; + 32 raw bits sync
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res = Decode(bit - 24 * 4 - 32 + 1, data[0])
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if res is not None:
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print "Systemcode", res[0], "onoff", res[1], "ch", res[2]
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../my-pi-projects/RaspyRFM/logilighttx.py
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37
logilighttx.py
Executable file
37
logilighttx.py
Executable file
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#!/usr/bin/env python2.7
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from rfm69 import Rfm69
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import rfm69
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import sys
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if len(sys.argv) != 5:
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print "usage: logiloghttx.py <systemcode> <channel> <on/off> <repetitions>"
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print "Example: logilighttx.py 65565 7 1 4"
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sys.exit(1)
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rfm = Rfm69()
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rfm.SetParams(
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Freq = 433.92,
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Datarate = 2.666666,
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TXPower = 13,
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ModulationType = rfm69.OOK,
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SyncPattern = []
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)
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#Frame generation
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def MakeFrame(systemcode, onoff, channel, rep):
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data = systemcode << 4 | onoff << 3 | channel
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frame = [0x00] * 12
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for i in range(24):
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if (data & (0x800000>>i)):
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nibble = 0xE0
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else:
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nibble = 0x80
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frame[i / 2] |= nibble >> (4 * (i % 2))
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frame += [0x80, 0x00, 0x00, 0x00] #sync
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return frame * rep
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data = MakeFrame(int(sys.argv[1]), int(sys.argv[2]), int(sys.argv[3]), int(sys.argv[4]))
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rfm.SendPacket(data)
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1
rfm69.py
1
rfm69.py
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../my-pi-projects/RaspyRFM/rfm69.py
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286
rfm69.py
Normal file
286
rfm69.py
Normal file
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import RPi.GPIO as GPIO
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import spidev
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import threading
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import time
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FXOSC = 32E6
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FSTEP = FXOSC / (1<<19)
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#------ Raspberry RFM Module connection -----
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# Connect RaspyRFM module to pins 17-26 on raspberry pi
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#-------------------------------------------------#
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# Raspi | Raspi | Raspi | RFM69 | RFM12 | PCB con #
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# Name | GPIO | Pin | Name | Name | Pin #
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#-------------------------------------------------#
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# 3V3 | - | 17 | 3.3V | VDD | 1 #
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# - | 24 | 18 | DIO1 | FFIT | 2 # only when PCB jumper closed, DIO0/nIRQ on 2nd modul!
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# MOSI | 10 | 19 | MOSI | SDI | 3 #
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# GND | - | 20 | GND | GND | 4 #
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# MISO | 9 | 21 | MISO | SDO | 5 #
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# - | 25 | 22 | DIO0 | nIRQ | 6 #
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# SCKL | 11 | 23 | SCK | SCK | 7 #
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# CE0 | 8 | 24 | NSS | nSEL | 8 #
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# CE1 | 7 | 26 | DIO2 | nFFS | 10 # only when PCB jumper closed, NSS/nFFS on 2nd modul!
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#-------------------------------------------------#
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#RFM69 registers
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RegFifo = 0x00
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RegOpMode = 0x01
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RegDataModul = 0x02
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RegBitrateMsb = 0x03
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RegBitrateLsb = 0x04
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RegFdevMsb = 0x05
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RegFdevLsb = 0x06
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RegFrMsb = 0x07
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RegFrMid = 0x08
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RegFrLsb = 0x09
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RegPaLevel = 0x11
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RegLna = 0x18
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RegRxBw = 0x19
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RegAfcBw = 0x1A
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RegAfcFei = 0x1E
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RegAfcMsb = 0x1F
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RegAfcLsb = 0x20
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RegFeiMsb = 0x21
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RegFeiLsb = 0x22
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RegRssiConfig = 0x23
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RegRssiValue = 0x24
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RegDioMapping1 = 0x25
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RegDioMapping2 = 0x26
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RegIrqFlags1 = 0x27
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RegIrqFlags2 = 0x28
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RegRssiThresh = 0x29
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RegPreambleMsb = 0x2C
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RegPreambleLsb = 0x2D
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RegSyncConfig = 0x2E
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RegSyncValue1 = 0x2F
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RegPacketConfig1 = 0x37
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RegPayloadLength = 0x38
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RegFifoThresh = 0x3C
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RegPacketConfig2 = 0x3D
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RegTestDagc = 0x6F
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InterPacketRxDelay = 4 #Bitposition
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RestartRx = 2
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AutoRxRestartOn = 1
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AesOn = 0
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#Modulation type
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OOK = 1
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FSK = 0
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#RFM69 modes
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MODE_SLEEP = 0
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MODE_STDBY = 1
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MODE_FS = 2
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MODE_TX = 3
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MODE_RX = 4
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class Rfm69:
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def __init__(self, cs = 0, gpio_int = 25):
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self.__event = threading.Event()
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self.__spi = spidev.SpiDev()
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self.__spi.open(0, cs)
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self.__spi.max_speed_hz=int(5E6)
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self.__gpio_int = gpio_int
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#Testing presence of module
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err = False
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for i in range(0, 8):
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self.__WriteReg(RegSyncValue1 + i, 0x55)
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if self.ReadReg(RegSyncValue1 + i) != 0x55:
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err = True
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break
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self.__WriteReg(RegSyncValue1 + i, 0xAA)
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if self.ReadReg(RegSyncValue1 + i) != 0xAA:
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err = True
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break
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if err == True:
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print "ERROR! RFM69 not found!"
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return
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print "RFM69 found!"
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GPIO.setmode(GPIO.BCM)
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GPIO.setup(gpio_int, GPIO.IN)
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GPIO.add_event_detect(gpio_int, GPIO.RISING, callback=self.__RfmIrq)
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self.__WriteReg(RegOpMode, MODE_STDBY << 2)
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self.__WaitMode()
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config = {}
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config[RegDataModul] = 0 #packet mode, modulation shaping, modulation
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config[RegPayloadLength] = 0
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config[RegPreambleMsb] = 0
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config[RegPreambleLsb] = 0
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config[RegSyncConfig] = 0 #sync off
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config[RegPacketConfig1] = 0x00 #Fixed length, CRC off, no adr
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config[RegPacketConfig2] = 0 #1<<AutoRxRestartOn
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config[RegAfcFei] = 1<<3 | 1<<1 | 0<<2 #AFC auto clear, clear AFC, afcAutoOn
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config[RegTestDagc] = 0x30
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config[RegRssiThresh] = 0x90
|
||||
config[RegFifoThresh] = 0x8F
|
||||
config[RegBitrateMsb] = 0x1A
|
||||
config[RegBitrateLsb] = 0x0B
|
||||
|
||||
for key in config:
|
||||
self.__WriteReg(key, config[key])
|
||||
|
||||
self.__WriteReg(RegOpMode, MODE_STDBY << 2)
|
||||
self.__WaitMode()
|
||||
|
||||
print("INIT COMPLETE")
|
||||
|
||||
def __RfmIrq(self, ch):
|
||||
self.__event.set();
|
||||
|
||||
def __WriteReg(self, reg, val):
|
||||
temp = self.__spi.xfer2([(reg & 0x7F) | 0x80, val & 0xFF])
|
||||
|
||||
def __WriteRegWord(self, reg, val):
|
||||
self.__WriteReg(reg, (val >> 8) & 0xFF)
|
||||
self.__WriteReg(reg + 1, val & 0xFF)
|
||||
|
||||
def __SetReg(self, reg, mask, val):
|
||||
temp = self.ReadReg(reg) & (~mask)
|
||||
temp |= val & mask
|
||||
self.__WriteReg(reg, temp)
|
||||
|
||||
def __SetDioMapping(self, dio, mapping):
|
||||
if ((dio >= 0) and (dio <=3)):
|
||||
self.__SetReg(RegDioMapping1, 0xC0 >> (dio * 2), mapping << (6 - dio * 2))
|
||||
elif (dio == 5):
|
||||
self.__SetReg(RegDioMapping2, 0x03 << 4, mapping << 4)
|
||||
|
||||
def ReadReg(self, reg):
|
||||
temp = self.__spi.xfer2([reg & 0x7F, 0x00])
|
||||
return temp[1]
|
||||
|
||||
def ReadRegWord(self, reg):
|
||||
temp = self.__spi.xfer2([reg & 0x7F, 0x00, 0x00])
|
||||
return (temp[1] << 8) | (temp[2])
|
||||
|
||||
def ReadRssiValue(self):
|
||||
self.__WriteReg(RegRssiConfig, 1)
|
||||
while ((self.ReadReg(RegRssiConfig) & (1<<1)) == 0):
|
||||
pass
|
||||
return self.ReadReg(RegRssiValue)
|
||||
|
||||
def SetParams(self, **params):
|
||||
for key in params:
|
||||
value = params[key]
|
||||
if key == "Freq":
|
||||
fword = int(round(value * 1E6 / FSTEP))
|
||||
self.__WriteReg(RegFrLsb, fword)
|
||||
self.__WriteReg(RegFrMid, fword >> 8)
|
||||
self.__WriteReg(RegFrMsb, fword >> 16)
|
||||
|
||||
elif key == "TXPower":
|
||||
pwr = int(value + 18)
|
||||
self.__WriteReg(RegPaLevel, 0x80 | (pwr & 0x1F))
|
||||
|
||||
elif key == "Datarate":
|
||||
rate = int(round(FXOSC / (value * 1000)))
|
||||
self.__WriteRegWord(RegBitrateMsb, rate)
|
||||
|
||||
elif key == "Deviation":
|
||||
dev = int(round(value * 1000 / FSTEP))
|
||||
self.__WriteRegWord(RegFdevMsb, dev)
|
||||
|
||||
elif key == "ModulationType":
|
||||
self.__SetReg(RegDataModul, 0x18, value << 3)
|
||||
|
||||
elif key == "ModulationsShaping":
|
||||
self.__SetReg(RegDataModul, 0x03, value)
|
||||
|
||||
elif key == "SyncPattern":
|
||||
conf = 0
|
||||
if (len(value)) > 0:
|
||||
conf = ((len(value) - 1) & 0x07) << 3
|
||||
conf |= 1<<7
|
||||
else:
|
||||
conf = 1<<6
|
||||
self.__WriteReg(RegSyncConfig, conf)
|
||||
for i, d in enumerate(value):
|
||||
self.__WriteReg(RegSyncValue1 + i, d)
|
||||
|
||||
elif key == "Bandwidth":
|
||||
RxBw = FXOSC / value / 1000 / 4
|
||||
e = 0
|
||||
while (RxBw > 32) and (e < 7):
|
||||
e += 1
|
||||
RxBw /= 2
|
||||
RxBw = RxBw / 4 - 4
|
||||
RxBw = max(RxBw, 0)
|
||||
m = int(RxBw)
|
||||
self.__SetReg(RegRxBw, 0x1F, m<<3 | e)
|
||||
self.__SetReg(RegAfcBw, 0x1F, m<<3 | e)
|
||||
|
||||
elif key == "Preamble":
|
||||
self.__WriteRegWord(RegPreambleMsb, value)
|
||||
|
||||
elif key == "LnaGain":
|
||||
self.__SetReg(RegLna, 0x03, value)
|
||||
|
||||
elif key == "RssiThresh":
|
||||
th = -(value * 2)
|
||||
self.__WriteReg(RegRssiThresh, th)
|
||||
|
||||
else:
|
||||
print("Unrecognized option >>" + key + "<<")
|
||||
|
||||
def __WaitMode(self):
|
||||
while ((self.ReadReg(RegIrqFlags1) & (1<<7)) == 0):
|
||||
pass
|
||||
|
||||
def SendPacket(self, data):
|
||||
self.__WriteReg(RegOpMode, MODE_STDBY << 2)
|
||||
self.__WaitMode()
|
||||
|
||||
#flush FIFO
|
||||
status = self.ReadReg(RegIrqFlags2)
|
||||
while (status & 0x40 == 0x40):
|
||||
self.ReadReg(RegFifo)
|
||||
status = self.ReadReg(RegIrqFlags2)
|
||||
|
||||
self.__WriteReg(RegPayloadLength, 0)
|
||||
self.__SetDioMapping(0, 0) # DIO0 -> PacketSent
|
||||
self.__WriteReg(RegOpMode, MODE_TX << 2) #TX Mode
|
||||
|
||||
for i, d in enumerate(data):
|
||||
self.__WriteReg(RegFifo, d)
|
||||
if i>60:
|
||||
status = self.ReadReg(RegIrqFlags2)
|
||||
#check FifoFull
|
||||
while (status & 0x80) == 0x80:
|
||||
status = self.ReadReg(RegIrqFlags2)
|
||||
|
||||
#wait packet sent
|
||||
self.__event.wait()
|
||||
self.__event.clear()
|
||||
self.__WriteReg(RegOpMode, MODE_STDBY << 2)
|
||||
self.__WaitMode()
|
||||
|
||||
def ReceivePacket(self, length):
|
||||
self.__WriteReg(RegPayloadLength, length)
|
||||
|
||||
self.__SetDioMapping(0, 2) #DIO0 -> SyncAddress
|
||||
self.__SetDioMapping(1, 3)
|
||||
self.__SetReg(RegOpMode, 7<<2, 4<<2) #RX mode
|
||||
|
||||
self.__event.wait()
|
||||
self.__event.clear()
|
||||
self.__SetDioMapping(0, 1) #DIO0 -> PayloaReady
|
||||
|
||||
rssi = -self.ReadReg(RegRssiValue) / 2
|
||||
self.__event.wait()
|
||||
self.__event.clear()
|
||||
|
||||
result = []
|
||||
for x in range(length):
|
||||
result.append(self.ReadReg(RegFifo))
|
||||
|
||||
self.__WriteReg(RegOpMode, 0) #idle mode
|
||||
|
||||
return (result, rssi)
|
||||
|
|
@ -1 +0,0 @@
|
|||
../my-pi-projects/RaspyRFM/sensors.py
|
||||
83
sensors.py
Normal file
83
sensors.py
Normal file
|
|
@ -0,0 +1,83 @@
|
|||
def crc8(buf):
|
||||
crc = 0
|
||||
for j in range(5):
|
||||
crc = crc ^ buf[j]
|
||||
for i in range(8):
|
||||
if (crc & 0x80 == 0x80):
|
||||
crc = (crc << 1) ^ 0x31
|
||||
else:
|
||||
crc <<= 1
|
||||
return crc & 0xFF
|
||||
|
||||
def csum(data):
|
||||
s = 0
|
||||
for i in range(12):
|
||||
s += data[i]
|
||||
return s & 0xFF
|
||||
|
||||
class rawsensor(object):
|
||||
def __init__(self, data):
|
||||
self._data = {}
|
||||
self.__raw = data
|
||||
|
||||
def __str__(self):
|
||||
res = 'RAW RSSI ' + str(self.__raw[1]) + " dBm: "
|
||||
for data in self.__raw[0]:
|
||||
res = res + ' ' + hex(data)[2:];
|
||||
return res;
|
||||
|
||||
def GetData(self):
|
||||
return self._data
|
||||
|
||||
@staticmethod
|
||||
def CreateSensor(data):
|
||||
obj = lacross.Create(data)
|
||||
if (obj):
|
||||
return obj
|
||||
|
||||
obj = emt7110.Create(data)
|
||||
if (obj):
|
||||
return obj
|
||||
|
||||
return rawsensor(data)
|
||||
|
||||
class lacross(rawsensor):
|
||||
def __init__(self, data):
|
||||
rawsensor.__init__(self, data)
|
||||
id = data[0][0] << 4 | data[0][1] >> 4
|
||||
print "A", hex(data[0][0])[2:], hex(data[0][1])[2:]
|
||||
self._data['ID'] = hex(id & 0xFC)[2:]
|
||||
self._data['init'] = bool(id & 1<<1)
|
||||
self._data['T'] = (10 * ((data[0][1] & 0xF) - 4) + (data[0][2] >> 4) + (data[0][2] & 0xF) / 10.0, 'C')
|
||||
rh = data[0][3] & 0x7F
|
||||
if rh <= 100:
|
||||
self._data['RH'] = (rh, '%')
|
||||
self._data['batlo'] = bool(rh & 1<<7)
|
||||
self._data['RSSI'] = data[1]
|
||||
|
||||
def __str__(self):
|
||||
res = 'La crosse ' + str(self._data) # + ' ' + rawsensor.__str__(self);
|
||||
return res;
|
||||
|
||||
@staticmethod
|
||||
def Create(data):
|
||||
if len(data[0]) >= 5 and len(data[0]) <= 8 and crc8(data[0]) == 0:
|
||||
return lacross(data)
|
||||
|
||||
class emt7110(rawsensor):
|
||||
def __init__(self, data):
|
||||
rawsensor.__init__(self, data)
|
||||
id = data[0] << 24 | data[1] << 16 | data[2] << 8 | data[3]
|
||||
self._data['ID'] = hex(id)[2:]
|
||||
self._data['P'] = (((data[4] << 8 | data[5]) & 0x3FFF) / 2.0, 'W')
|
||||
self._data['U'] = (data[8] / 2.0 + 128, 'V')
|
||||
self._data['I'] = (data[6] << 8 | data[7], 'mA')
|
||||
self._data['W'] = (((data[9] << 8 | data[10]) & 0x3FFF) / 100, 'kWh')
|
||||
|
||||
def __str__(self):
|
||||
return 'emt7110 ' + str(self._data)
|
||||
|
||||
@staticmethod
|
||||
def Create(data):
|
||||
if len(data) >= 12 and len(data) <= 20 and csum(data) == 0:
|
||||
return emt7110(data)
|
||||
Loading…
Reference in a new issue