add pinouts
use FIFO burst transfers fix hangups add whitening routines add DcFree options
This commit is contained in:
S. Seegel
parent
8562a1520b
commit
685c53e2ff
1 changed files with 108 additions and 52 deletions
160
rfm69.py
160
rfm69.py
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@ -6,22 +6,58 @@ import time
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FXOSC = 32E6
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FSTEP = FXOSC / (1<<19)
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#------ Raspberry RFM Module connection -----
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# Connect RaspyRFM module to pins 17-26 on raspberry pi
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# RaspyRFM single module
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# Connect to pins 17-26 on raspberry pi
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#-------------------------------------------------#
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# Raspi | Raspi | Raspi | RFM69 | RFM12 | PCB con #
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# Name | GPIO | Pin | Name | Name | Pin #
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#-------------------------------------------------#
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# 3V3 | - | 17 | 3.3V | VDD | 1 #
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# - | 24 | 18 | DIO1 | FFIT | 2 # only when PCB jumper closed, DIO0/nIRQ on 2nd modul!
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# - | 24 | 18 | DIO1 | FFIT | 2 # only when PCB jumper closed
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# MOSI | 10 | 19 | MOSI | SDI | 3 #
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# GND | - | 20 | GND | GND | 4 #
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# MISO | 9 | 21 | MISO | SDO | 5 #
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# - | 25 | 22 | DIO0 | nIRQ | 6 #
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# SCKL | 11 | 23 | SCK | SCK | 7 #
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# CE0 | 8 | 24 | NSS | nSEL | 8 #
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# CE1 | 7 | 26 | DIO2 | nFFS | 10 # only when PCB jumper closed, NSS/nFFS on 2nd modul!
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# CE1 | 7 | 26 | DIO2 | nFFS | 10 # only when PCB jumper closed
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#-------------------------------------------------#
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# RaspyRFM twin module with 10-pin connector
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# Connect to pins 17-26 on raspberry pi
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#-------------------------------------------------#
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# Raspi | Raspi | Raspi | RFM69 | RFM12 | PCB con #
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# Name | GPIO | Pin | Name | Name | Pin #
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#-------------------------------------------------#
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# 3V3 | - | 17 | 3.3V | VDD | 1 #
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# - | 24 | 18 | DIO0_2| FFIT | 2 #
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# MOSI | 10 | 19 | MOSI | SDI | 3 #
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# GND | - | 20 | GND | GND | 4 #
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# MISO | 9 | 21 | MISO | SDO | 5 #
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# - | 25 | 22 | DIO0_1| nIRQ | 6 #
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# SCKL | 11 | 23 | SCK | SCK | 7 #
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# CE0 | 8 | 24 | NSS1 | nSEL | 8 #
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# CE1 | 7 | 26 | NSS2 | nFFS | 10 #
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#-------------------------------------------------#
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# RaspyRFM twin module with 12-pin connector
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# Connect to pins 15-26 on raspberry pi
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#-------------------------------------------------#
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# Raspi | Raspi | Raspi | RFM69 | RFM12 | PCB con #
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# Name | GPIO | Pin | Name | Name | Pin #
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#-------------------------------------------------#
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# - | 22 | 15 | DIO2_2| | 1 #
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# - | 23 | 16 | DIO2_1| | 2 #
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# 3V3 | - | 17 | 3.3V | VDD | 3 #
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# - | 24 | 18 | DIO0_2| FFIT | 4 #
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# MOSI | 10 | 19 | MOSI | SDI | 5 #
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# GND | - | 20 | GND | GND | 6 #
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# MISO | 9 | 21 | MISO | SDO | 7 #
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# - | 25 | 22 | DIO0_1| nIRQ | 8 #
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# SCKL | 11 | 23 | SCK | SCK | 9 #
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# CE0 | 8 | 24 | NSS1 | nSEL | 10 #
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# CE1 | 7 | 26 | NSS2 | nFFS | 12 #
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#-------------------------------------------------#
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#RFM69 registers
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@ -107,6 +143,16 @@ MODE_FS = 2
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MODE_TX = 3
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MODE_RX = 4
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#DIO packet mode
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DIO0_PM_CRC = 0
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DIO0_PM_PAYLOAD = 1
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DIO0_PM_SYNC = 2
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DIO0_PM_RSSI = 3
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DIO0_PM_SENT = 0
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DIO0_PM_TXDONE = 1
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DIO0_PM_PLLLOCK = 3
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class Rfm69(threading.Thread):
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@staticmethod
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def Test(cs):
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@ -141,10 +187,10 @@ class Rfm69(threading.Thread):
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self.__spi.max_speed_hz=int(5E6)
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self.__gpio_int = gpio_int
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self.__mutex = threading.Lock()
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self.__rxmode = False
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self.__syncsize = 4
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self.__fifothresh = 32
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print "RFM69 found on CS", cs
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print("RFM69 found on CS " + str(cs))
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GPIO.setmode(GPIO.BCM)
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GPIO.setup(gpio_int, GPIO.IN)
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GPIO.add_event_detect(gpio_int, GPIO.RISING, callback=self.__RfmIrq)
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@ -176,7 +222,7 @@ class Rfm69(threading.Thread):
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config[RegLna] = 0x88
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config[RegRxBw] = 0x55
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config[RegAfcBw] = 0x8B
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config[RegOokPeak] = 0x40
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config[RegOokPeak] = 0x40
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config[RegOokAvg] = 0x80
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config[RegOokFix] = 0x06
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config[RegAfcFei] = 0x00
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@ -212,7 +258,6 @@ class Rfm69(threading.Thread):
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config[RegPacketConfig2] = 0 #1<<AutoRxRestartOn
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for key in config:
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v = self.ReadReg(key)
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self.__WriteReg(key, config[key])
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self.ModeStandBy()
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@ -246,6 +291,7 @@ class Rfm69(threading.Thread):
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def __SetMode(self, mode):
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self.__WriteReg(RegOpMode, mode << 2)
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self.__mode = mode
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while ((self.ReadReg(RegIrqFlags1) & (1<<7)) == 0):
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pass
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@ -253,6 +299,13 @@ class Rfm69(threading.Thread):
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temp = self.__spi.xfer2([reg & 0x7F, 0x00])
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return temp[1]
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def ReadFifoBurst(self, len):
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temp = self.__spi.xfer2([0x00] + [0x00] * len)
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return temp[1:]
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def WriteFifoBurst(self, data):
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self.__spi.xfer2([0x80] + data)
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def ReadRegWord(self, reg):
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temp = self.__spi.xfer2([reg & 0x7F, 0x00, 0x00])
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return (temp[1] << 8) | (temp[2])
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@ -260,12 +313,8 @@ class Rfm69(threading.Thread):
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def ReadRssiValue(self):
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self.__WriteReg(RegRssiConfig, 1<<0)
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r = self.ReadReg(RegRssiConfig)
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#print(hex(r))
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while ((r & (1<<1)) == 0):
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# print(hex(r))
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r = self.ReadReg(RegRssiConfig)
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# time.sleep(0.05)
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pass
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return self.ReadReg(RegRssiValue)
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def ModeStandBy(self):
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@ -353,15 +402,12 @@ class Rfm69(threading.Thread):
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elif key == "Callback":
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self.__Callback = value
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elif key == "CallbackSync":
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self.__CallbackSync = value
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elif key == "DcFree":
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self.__SetReg(RegPacketConfig1, 3<<5, value<<5)
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elif key == "OokThreshType":
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self.__SetReg(RegOokPeak, 3<<6, value<<6)
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elif key == "OokFixedThresh":
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self.__WriteReg(RegOokFix, value)
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@ -369,18 +415,16 @@ class Rfm69(threading.Thread):
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print("Unrecognized option >>" + key + "<<")
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self.ModeStandBy();
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self.__rxmode = False
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self.__mutex.release()
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def __WaitInt(self):
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self.__event.clear()
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if GPIO.input(self.__gpio_int):
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return
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while not self.__event.wait(0.1):
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while not self.__event.wait(0.5):
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if GPIO.input(self.__gpio_int):
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print("GPIO high!")
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break
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def WhitenHope(self, data):
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lfsr = 0x3fe
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for i, d in enumerate(data):
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@ -391,7 +435,7 @@ class Rfm69(threading.Thread):
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lfsr |= 1<<0
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lfsr <<= 1
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lfsr &= 0x3ff
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def WhitenTI(self, data):
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lfsr = 0x1ff
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for i, d in enumerate(data):
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@ -412,40 +456,49 @@ class Rfm69(threading.Thread):
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self.ReadReg(RegFifo)
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status = self.ReadReg(RegIrqFlags2)
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self.__WriteReg(RegPayloadLength, 0)
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self.__SetDioMapping(0, 0) #DIO0 -> PacketSent
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self.__WriteReg(RegOpMode, MODE_TX << 2) #TX Mode
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self.__WriteReg(RegPayloadLength, 0) #unlimited length
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self.__WriteReg(RegFifoThresh, 0x80 | self.__fifothresh) #start TX with 1st byte in FIFO
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self.__SetDioMapping(0, DIO0_PM_SENT) #DIO0 -> PacketSent
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self.__SetMode(MODE_TX)
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for i, d in enumerate(data):
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self.__WriteReg(RegFifo, d)
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if i>60:
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l = min(len(data), 64)
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while True:
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self.WriteFifoBurst(data[:l])
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data = data[l:]
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if len(data) == 0:
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break
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while True:
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status = self.ReadReg(RegIrqFlags2)
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#check FifoFull
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while (status & 0x80) == 0x80:
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status = self.ReadReg(RegIrqFlags2)
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if (status & (1<<5)) == 0: #below fifothresh
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l = min(len(data), self.__fifothresh)
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break
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if (status & (1<<7)) == 0: #space for at least 1 bytearray
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l = 1
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break
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#wait packet sent
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self.__WaitInt()
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self.ModeStandBy()
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self.__rxmode = False
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self.__mutex.release()
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def ReadFifoWait(self, length):
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ret = []
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while length > 0:
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flags = self.ReadReg(RegIrqFlags2)
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if ((flags & (1<<5)) != 0) and (length >= 32): #FIFO level?
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ret += self.ReadFifoBurst(self.__fifothresh)
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length -= self.__fifothresh
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if (flags & (1<<6)) != 0: #FIFO not empty?
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ret.append(self.ReadReg(RegFifo))
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length -= 1
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return ret
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def GetNoiseFloor(self):
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self.__mutex.acquire()
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#save values
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rssithresh = self.ReadReg(RegRssiThresh)
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ookthresh = self.ReadReg(RegOokFix)
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sync = self.ReadReg(RegSyncConfig)
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self.__WriteReg(RegRssiThresh, 240)
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self.__WriteReg(RegSyncConfig, 1<<6) #no sync, always fill FIFO
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self.__WriteReg(RegPayloadLength, 0) #unlimited length
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@ -460,7 +513,7 @@ class Rfm69(threading.Thread):
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break;
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if i == 149:
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break;
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#restore registers
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self.__WriteReg(RegRssiThresh, rssithresh)
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self.__WriteReg(RegOokFix, ookthresh)
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@ -469,37 +522,40 @@ class Rfm69(threading.Thread):
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self.__mutex.release()
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return thresh
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def ReceivePacket(self, length):
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def __StartRx(self):
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self.__SetDioMapping(2, 1) #DIO2 -> DATA
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self.__mutex.acquire()
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while True:
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self.__WriteReg(RegPayloadLength, length)
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self.__WriteReg(RegPayloadLength, 0) #unlimited lendth
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self.__WriteReg(RegFifoThresh, self.__fifothresh)
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if self.__syncsize > 0:
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self.__SetDioMapping(0, 2) #DIO0 -> SyncAddress
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self.__SetDioMapping(0, DIO0_PM_SYNC) #DIO0 -> SyncAddress
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else:
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self.__SetDioMapping(0, 3) #DIO0 -> RSSI
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print("goto rx")
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self.__SetDioMapping(0, DIO0_PM_RSSI) #DIO0 -> RSSI
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self.__SetMode(MODE_RX)
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self.__rxmode = True
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self.__mutex.release()
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self.__WaitInt()
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self.__mutex.acquire()
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if self.__rxmode == True:
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if self.__mode == MODE_RX:
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break;
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rssi = -self.ReadReg(RegRssiValue) / 2
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def StartRx(self, cb):
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self.__StartRx()
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cb()
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self.ModeStandBy()
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self.__mutex.release()
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def ReceivePacket(self, length):
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self.__StartRx()
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afc = self.ReadReg(RegAfcMsb) << 8
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afc = afc | self.ReadReg(RegAfcLsb)
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if afc >= 0x8000:
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afc = afc - 0x10000
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if hasattr(self, "_Rfm69__CallbackSync"):
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self.__CallbackSync()
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self.ModeStandBy()
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self.__mutex.release()
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return
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result = self.ReadFifoWait(length)
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rssi = -self.ReadReg(RegRssiValue) / 2
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if afc >= 0x8000:
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afc = afc - 0x10000
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self.ModeStandBy()
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self.__mutex.release()
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return (result, rssi, afc)
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return (result, rssi, afc)
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