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S. Seegel
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2
README.md
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README.md
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Python files for RaspyRFM
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rfm69.py
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rfm69.py
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import RPi.GPIO as GPIO
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import spidev
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import threading
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import time
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FXOSC = 32E6
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FSTEP = FXOSC / (1<<19)
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#------ Raspberry RFM Module connection -----
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#
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#-------------------------------------------------#
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# Raspi | Raspi | Raspi | RFM69 | RFM12 | PCB con #
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# Name | GPIO | Pin | Name | Name | Pin #
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#-------------------------------------------------#
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# 3V3 | - | 17 | 1
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# - | 24 | 18 | DIO1 | FFIT | 2
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# MOSI | 10 | 19 | MOSI | SDI | 3
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# GND | - | 20 | GND | GND | 4
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# MISO | 9 | 21 | MISO | SDO | 5
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# - | 25 | 22 | DIO0 | nIRQ | 6
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# SCKL | 11 | 23 | SCK | SCK | 7
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# CE0 | 8 | 24 | NSS | nSEL | 8
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# CE1 | 7 | 26 | DIO2 | nFFS | 10
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#--------------------------------------------
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#RFM69 registers
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RegFifo = 0x00
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RegOpMode = 0x01
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RegDataModul = 0x02
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RegBitrateMsb = 0x03
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RegBitrateLsb = 0x04
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RegFdevMsb = 0x05
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RegFdevLsb = 0x06
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RegFrMsb = 0x07
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RegFrMid = 0x08
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RegFrLsb = 0x09
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RegPaLevel = 0x11
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RegLna = 0x18
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RegRxBw = 0x19
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RegAfcBw = 0x1A
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RegAfcFei = 0x1E
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RegAfcMsb = 0x1F
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RegAfcLsb = 0x20
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RegFeiMsb = 0x21
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RegFeiLsb = 0x22
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RegRssiConfig = 0x23
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RegRssiValue = 0x24
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RegDioMapping1 = 0x25
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RegDioMapping2 = 0x26
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RegIrqFlags1 = 0x27
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RegIrqFlags2 = 0x28
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RegRssiThresh = 0x29
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RegPreambleMsb = 0x2C
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RegPreambleLsb = 0x2D
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RegSyncConfig = 0x2E
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RegSyncValue1 = 0x2F
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RegPacketConfig1 = 0x37
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RegPayloadLength = 0x38
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RegFifoThresh = 0x3C
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RegPacketConfig2 = 0x3D
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RegTestDagc = 0x6F
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InterPacketRxDelay = 4 #Bitposition
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RestartRx = 2
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AutoRxRestartOn = 1
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AesOn = 0
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#Modulation type
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OOK = 1
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FSK = 0
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#RFM69 modes
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MODE_SLEEP = 0
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MODE_STDBY = 1
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MODE_FS = 2
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MODE_TX = 3
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MODE_RX = 4
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class Rfm69:
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def __init__(self, spiport = 0, gpio_int = 25):
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self.__event = threading.Event()
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self.__spi = spidev.SpiDev()
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self.__spi.open(0, spiport)
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self.__spi.max_speed_hz=int(5E6)
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self.__gpio_int = gpio_int
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#Testing presence of module
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err = False
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for i in range(0, 8):
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self.__WriteReg(RegSyncValue1 + i, 0x55)
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if self.ReadReg(RegSyncValue1 + i) != 0x55:
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err = True
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break
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self.__WriteReg(RegSyncValue1 + i, 0xAA)
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if self.ReadReg(RegSyncValue1 + i) != 0xAA:
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err = True
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break
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if err == True:
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print "ERROR! RFM69 not found!"
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return
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print "RFM69 found!"
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GPIO.setmode(GPIO.BCM)
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GPIO.setup(gpio_int, GPIO.IN)
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GPIO.add_event_detect(gpio_int, GPIO.RISING, callback=self.__RfmIrq)
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self.__WriteReg(RegOpMode, MODE_STDBY << 2)
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self.__WaitMode()
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config = {}
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config[RegDataModul] = 0 #packet mode, modulation shaping, modulation
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config[RegPayloadLength] = 0
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config[RegPreambleMsb] = 0
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config[RegPreambleLsb] = 0
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config[RegSyncConfig] = 0 #sync off
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config[RegPacketConfig1] = 0x00 #Fixed length, CRC off, no adr
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config[RegPacketConfig2] = 0 #1<<AutoRxRestartOn
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config[RegAfcFei] = 1<<3 | 1<<1 | 0<<2 #AFC auto clear, clear AFC, afcAutoOn
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config[RegTestDagc] = 0x30
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config[RegRssiThresh] = 0xE0
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config[RegFifoThresh] = 0x8F
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for key in config:
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self.__WriteReg(key, config[key])
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print("INIT COMPLETE")
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def __RfmIrq(self, ch):
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print("IRQ!")
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self.__event.set();
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def __WriteReg(self, reg, val):
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temp = self.__spi.xfer2([(reg & 0x7F) | 0x80, val & 0xFF])
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def __WriteRegWord(self, reg, val):
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self.__WriteReg(reg, (val >> 8) & 0xFF)
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self.__WriteReg(reg + 1, val & 0xFF)
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def __SetReg(self, reg, mask, val):
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temp = self.ReadReg(reg) & (~mask)
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temp |= val & mask
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self.__WriteReg(reg, temp)
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def __SetDioMapping(self, dio, mapping):
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if ((dio >= 0) and (dio <=3)):
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self.__SetReg(RegDioMapping1, 0xC0 >> (dio * 2), mapping << (6 - dio * 2))
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elif (dio == 5):
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self.__SetReg(RegDioMapping2, 0x03 << 4, mapping << 4)
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def ReadReg(self, reg):
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temp = self.__spi.xfer2([reg & 0x7F, 0x00])
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return temp[1]
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def ReadRegWord(self, reg):
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temp = self.__spi.xfer2([reg & 0x7F, 0x00, 0x00])
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return (temp[1] << 8) | (temp[2])
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def ReadRssiValue(self):
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self.__WriteReg(RegRssiConfig, 1)
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while ((self.ReadReg(RegRssiConfig) & (1<<1)) == 0):
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pass
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return self.ReadReg(RegRssiValue)
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def SetParams(self, **params):
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for key in params:
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value = params[key]
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if key == "Freq":
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fword = int(round(value * 1E6 / FSTEP))
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self.__WriteReg(RegFrLsb, fword)
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self.__WriteReg(RegFrMid, fword >> 8)
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self.__WriteReg(RegFrMsb, fword >> 16)
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elif key == "TXPower":
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pwr = int(value + 18)
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self.__WriteReg(RegPaLevel, 0x80 | (pwr & 0x1F))
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elif key == "Datarate":
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rate = int(round(FXOSC / (value * 1000)))
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self.__WriteRegWord(RegBitrateMsb, rate)
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elif key == "Deviation":
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dev = int(round(value * 1000 / FSTEP))
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self.__WriteRegWord(RegFdevMsb, dev)
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elif key == "ModulationType":
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self.__SetReg(RegDataModul, 0x18, value << 3)
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elif key == "ModulationsShaping":
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self.__SetReg(RegDataModul, 0x03, value)
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elif key == "SyncPattern":
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conf = ((len(value) - 1) & 0x07) << 3
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if (len(value)) > 0:
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conf |= 1<<7
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self.__WriteReg(RegSyncConfig, conf)
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for i, d in enumerate(value):
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self.__WriteReg(RegSyncValue1 + i, d)
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elif key == "Bandwidth":
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RxBw = FXOSC / value / 1000 / 4
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e = 0
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while (RxBw > 32) and (e < 7):
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e += 1
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RxBw /= 2
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RxBw = RxBw / 4 - 4
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RxBw = max(RxBw, 0)
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m = int(RxBw)
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self.__SetReg(RegRxBw, 0x1F, m<<3 | e)
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self.__SetReg(RegAfcBw, 0x1F, m<<3 | e)
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elif key == "Preamble":
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self.__WriteRegWord(RegPreambleMsb, value)
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elif key == "LnaGain":
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self.__SetReg(RegLna, 0x03, value)
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else:
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print("Unrecognized option >>" + key + "<<")
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def __WaitMode(self):
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while ((self.ReadReg(RegIrqFlags1) & (1<<7)) == 0):
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pass
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def SendPacket(self, data):
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self.__WriteReg(RegOpMode, MODE_STDBY << 2)
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self.__WaitMode()
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#flush FIFO
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status = self.ReadReg(RegIrqFlags2)
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while (status & 0x40 == 0x40):
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self.ReadReg(RegFifo)
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status = self.ReadReg(RegIrqFlags2)
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self.__WriteReg(RegPayloadLength, 30)
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self.__SetDioMapping(0, 0) # DIO0 -> PacketSent
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self.__SetDioMapping(1, 2) # DIO1 -> FifoNotEmpty
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self.__WriteReg(RegOpMode, MODE_TX << 2) #TX Mode
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for i, d in enumerate(data):
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self.__WriteReg(RegFifo, d)
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if i>60:
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status = self.ReadReg(RegIrqFlags2)
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#check FifoFull
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while (status & 0x80) == 0x80:
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status = self.ReadReg(RegIrqFlags2)
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#wait packet sent
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status = self.ReadReg(RegIrqFlags2)
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while (status & 0x08) == 0x00:
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status = self.ReadReg(RegIrqFlags2)
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#print ("s ", hex(status))
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self.__WriteReg(RegOpMode, MODE_STDBY << 2)
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self.__WaitMode()
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return
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time.sleep(1)
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self.__WriteReg(RegOpMode, MODE_TX << 2) #TX Mode
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for d in [1, 2, 3, 4, 5]:
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status = self.ReadReg(RegIrqFlags2)
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#print "Status: ", hex(status)
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#check FifoFull
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#while (status & 0x80) == 0x80:
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# status = self.ReadReg(RegIrqFlags2)
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#self.__WriteReg(RegFifo, d)
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#for x in range(16):
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# self.__WriteReg(RegFifo, 0x55)
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#self.__event.wait()
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#self.__event.clear()
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#check PacketSent
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status = self.ReadReg(RegIrqFlags2)
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while (status & 0x08) == 0x00:
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#print "Status: ", hex(self.ReadReg(RegIrqFlags2))
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status = self.ReadReg(RegIrqFlags2)
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self.__WriteReg(RegOpMode, 0) #idle mode
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self.__WaitMode()
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def ReceivePacket(self, length):
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self.__WriteReg(RegPayloadLength, length)
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self.__SetDioMapping(0, 1) #DIO0 -> PayloadReady
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self.__SetDioMapping(1, 3)
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self.__SetReg(RegOpMode, 7<<2, 4<<2) #RX mode
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self.__event.wait()
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self.__event.clear()
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result = []
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for x in range(length):
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result.append(self.ReadReg(RegFifo))
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self.__WriteReg(RegOpMode, 0) #idle mode
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return result
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