add MAX! receiving
add variable packet length
This commit is contained in:
S. Seegel
parent
160cf40b99
commit
d61c88d4dc
2 changed files with 47 additions and 35 deletions
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@ -1,7 +1,6 @@
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#!/usr/bin/env python2.7
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from rfm69 import Rfm69
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import rfm69
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from raspyrfm import *
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import sys
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import time
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import threading
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@ -16,23 +15,23 @@ devices = {
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'0x1ac36b': 'HeatWohnL',
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}
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if Rfm69.Test(1):
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if raspyrfm_test(2, RFM69):
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print("Found RaspyRFM twin")
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rfm = Rfm69(1, 24) #when using the RaspyRFM twin
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elif Rfm69.Test(0):
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rfm = RaspyRFM(2, RFM69) #when using the RaspyRFM twin
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elif raspyrfm_test(1, RFM69):
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print("Found RaspyRFM single")
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rfm = Rfm69() #when using a single single 868 MHz RaspyRFM
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rfm = RaspyRFM(1, RFM69) #when using a single single 868 MHz RaspyRFM
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else:
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print("No RFM69 module found!")
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exit()
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rfm.SetParams(
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rfm.set_params(
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Freq = 868.300, #MHz center frequency
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ModulationType = rfm69.FSK, #modulation
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Datarate = 9.992, #kbit/s baudrate
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Deviation = 19.042, #kHz frequency deviation
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SyncPattern = [0xc6, 0x26, 0xc6, 0x26], #syncword
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Bandwidth = 100, #kHz bandwidth
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Bandwidth = 150, #kHz bandwidth
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RssiThresh = -105, #dBm RSSI threshold
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)
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@ -45,10 +44,10 @@ class RxThread(threading.Thread):
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self.__rfm = rfm
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threading.Thread.__init__(self)
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def __callback(self):
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frame = rfm.ReadFifoWait(1)
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def __callback(self, rfm):
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frame = rfm.read_fifo_wait(1)
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len = frame[0] ^ 0xFF #invert due to whitening
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frame += rfm.ReadFifoWait(len)
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frame += rfm.read_fifo_wait(len)
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rxMutex.acquire()
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rxFifo.append(frame)
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@ -57,7 +56,7 @@ class RxThread(threading.Thread):
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def run(self):
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while True:
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self.__rfm.StartRx(self.__callback)
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self.__rfm.start_receive(self.__callback)
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rxThread = RxThread(rfm)
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@ -122,7 +121,7 @@ while True:
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left = len(rxFifo) > 0
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rxMutex.release()
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rfm.WhitenTI(frame)
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rfm.whiten_ti(frame)
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Decode(frame)
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if not left:
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break
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@ -43,22 +43,22 @@ FSTEP = FXOSC / (1<<19)
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# RaspyRFM twin module with 12-pin connector
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# Connect to pins 15-26 on raspberry pi
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#-------------------------------------------------#
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# Raspi | Raspi | Raspi | RFM69 | RFM12 | PCB con #
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# Name | GPIO | Pin | Name | Name | Pin #
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#-------------------------------------------------#
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# - | 22 | 15 | DIO2_2| | 1 #
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# - | 23 | 16 | DIO2_1| | 2 #
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# 3V3 | - | 17 | 3.3V | VDD | 3 #
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# - | 24 | 18 | DIO0_2| FFIT | 4 #
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# MOSI | 10 | 19 | MOSI | SDI | 5 #
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# GND | - | 20 | GND | GND | 6 #
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# MISO | 9 | 21 | MISO | SDO | 7 #
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# - | 25 | 22 | DIO0_1| nIRQ | 8 #
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# SCKL | 11 | 23 | SCK | SCK | 9 #
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# CE0 | 8 | 24 | NSS1 | nSEL | 10 #
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# CE1 | 7 | 26 | NSS2 | nFFS | 12 #
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#-------------------------------------------------#
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#---------------------------------#
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#Raspi|Raspi|Raspi|RFM69 |RaspyRFM#
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#Name |GPIO |Pin |Name |PCB Pin #
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#---------------------------------#
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# - | 22 | 15 |DIO2_2| 1 #
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# - | 23 | 16 |DIO2_1| 2 #
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#3V3 | - | 17 |3.3V | 3 #
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# - | 24 | 18 |DIO0_2| 4 #
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#MOSI | 10 | 19 |MOSI | 5 #
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#GND | - | 20 |GND | 6 #
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#MISO | 9 | 21 |MISO | 7 #
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# - | 25 | 22 |DIO0_1| 8 #
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#SCKL | 11 | 23 |SCK | 9 #
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#CE0 | 8 | 24 |NSS1 | 10 #
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#CE1 | 7 | 26 |NSS2 | 12 #
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#---------------------------------#
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#RFM69 registers
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#common registers
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@ -152,6 +152,10 @@ DIO0_PM_SENT = 0
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DIO0_PM_TXDONE = 1
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DIO0_PM_PLLLOCK = 3
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#Packet format
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PacketFormat_Fixed = 0
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PacketFormat_Variable = 1
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class Rfm69(threading.Thread):
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@staticmethod
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def test(cs, gpio_dio0):
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@ -187,6 +191,7 @@ class Rfm69(threading.Thread):
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self.__mutex = threading.Lock()
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self.__syncsize = 4
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self.__fifothresh = 32
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self.__packet_format = PacketFormat_Fixed
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print("RFM69 found on CS " + str(cs))
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GPIO.setmode(GPIO.BCM)
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@ -407,6 +412,10 @@ class Rfm69(threading.Thread):
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elif key == "OokPeakThreshDec":
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self.__set_reg(RegOokPeak, 7<<0, value)
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elif key == "PacketFormat":
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self.__set_reg(RegPacketConfig1, 1<<7, value<<7)
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self.__packet_format = value
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else:
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print("Unrecognized option >>" + key + "<<")
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@ -451,8 +460,10 @@ class Rfm69(threading.Thread):
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while (status & 0x40 == 0x40):
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self.read_reg(RegFifo)
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status = self.read_reg(RegIrqFlags2)
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self.__write_reg(RegPayloadLength, 0) #unlimited length
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if self.__packet_format == PacketFormat_Variable:
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data.insert(0, len(data))
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else:
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self.__write_reg(RegPayloadLength, 0) #unlimited length
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self.__write_reg(RegFifoThresh, 0x80 | self.__fifothresh) #start TX with 1st byte in FIFO
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self.__set_dio_mapping(0, DIO0_PM_SENT) #DIO0 -> PacketSent
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self.__set_mode(MODE_TX)
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@ -518,10 +529,10 @@ class Rfm69(threading.Thread):
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self.__mutex.release()
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return thresh
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def __start_rx(self):
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def __start_rx(self, length):
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self.__mutex.acquire()
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while True:
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self.__write_reg(RegPayloadLength, 0) #unlimited length
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self.__write_reg(RegPayloadLength, length)
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self.__write_reg(RegFifoThresh, self.__fifothresh)
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if self.__syncsize > 0:
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self.__set_dio_mapping(0, DIO0_PM_SYNC) #DIO0 -> SyncAddress
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@ -535,13 +546,15 @@ class Rfm69(threading.Thread):
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break;
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def start_receive(self, cb):
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self.__start_rx()
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self.__start_rx(0)
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cb(self)
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self.mode_standby()
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self.__mutex.release()
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def receive(self, length):
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self.__start_rx()
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self.__start_rx(length)
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if self.__packet_format == PacketFormat_Variable:
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length = self.read_fifo_wait(1)[0]
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result = self.read_fifo_wait(length)
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rssi = -self.read_reg(RegRssiValue) / 2
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