diff --git a/connair.py b/connair.py
deleted file mode 100755
index b1938ba..0000000
--- a/connair.py
+++ /dev/null
@@ -1,25 +0,0 @@
-#!/usr/bin/env python2.7
-
-import socket
-
-UDP_IP = "0.0.0.0"
-UDP_PORT = 49880
-HELLO_MESSAGE = "HCGW:VC:Seegel Systeme;MC:RaspyRFM;FW:1.00;IP:192.168.2.124;;"
-
-sock = socket.socket(socket.AF_INET, # Internet
-                     socket.SOCK_DGRAM) # UDP
-sock.bind((UDP_IP, UDP_PORT))
- 
-while True:
-  data, addr = sock.recvfrom(1024) # buffer size is 1024 bytes
-  msg = str(data).split(":")
-
-  print "received message:", msg, "from ", addr
-
-  if msg[0] == "SEARCH HCGW":
-    sock.sendto(HELLO_MESSAGE, addr)
-    print "Hello message"
-
-  if msg[0] == "TXP":
-    cmd = msg[1].split(",")
-    print "Command: ", cmd
diff --git a/intertechno.py b/intertechno.py
old mode 100644
new mode 100755
index c15b663..624fce0
--- a/intertechno.py
+++ b/intertechno.py
@@ -6,7 +6,8 @@ import sys
 import time
 
 if len(sys.argv) != 2:
-    print "usage: intertechno <CODE>" #12-digit code 12 * ['0', '1', 'f']
+    print "usage: intertechno <CODE>" #12-digit code 12 * ['0' | '1' | 'f']
+    print "Example: intertechno 0FF0F0F00FF0"
     sys.exit(1)
 
 rfm = Rfm69()
@@ -15,13 +16,14 @@ rfm.SetParams(
     Datarate = 2.666666,
     TXPower = 13,
     ModulationType = rfm69.OOK,
-    SyncPattern = [0x80, 0x00, 0x00, 0x00]
+    SyncPattern = []
     )
 
 #Frame generation
 def MakeFrame(code, rep):
     data = [0x80, 0x00, 0x00, 0x00] #sync
     b = 0;
+    data = []
     for c in code:
         if c == '0':
             data.append(0x88)
@@ -29,11 +31,9 @@ def MakeFrame(code, rep):
             data.append(0xEE)
         elif c == 'F' or c == 'f':
             data.append(0x8E)
+    data += [0x80, 0x00, 0x00, 0x00] #sync
         
-    result = []
-    for i in range(rep):
-        result += data
-    return result
+    return data * rep
 
-data = MakeFrame(sys.argv[1], 3)
+data = MakeFrame(sys.argv[1], 8)
 rfm.SendPacket(data)
diff --git a/rfm69.py b/rfm69.py
index ff185e4..a3a921f 100644
--- a/rfm69.py
+++ b/rfm69.py
@@ -105,11 +105,7 @@ class Rfm69:
         GPIO.setmode(GPIO.BCM)
         GPIO.setup(gpio_int, GPIO.IN)
         GPIO.add_event_detect(gpio_int, GPIO.RISING, callback=self.__RfmIrq)
-        
-        
-        self.__WriteReg(RegOpMode, MODE_STDBY << 2)
-        self.__WaitMode()
-        
+                
         config = {}
         config[RegDataModul] = 0 #packet mode, modulation shaping, modulation
         config[RegPayloadLength] = 0
@@ -122,14 +118,19 @@ class Rfm69:
         config[RegTestDagc] = 0x30
         config[RegRssiThresh] = 0xE0
         config[RegFifoThresh] = 0x8F
+        config[RegBitrateMsb] = 0x1A
+        config[RegBitrateLsb] = 0x0B
         
         for key in config:
             self.__WriteReg(key, config[key])
             
+        self.__WriteReg(RegOpMode, MODE_STDBY << 2)
+        self.__WaitMode()
+
         print("INIT COMPLETE")
     
     def __RfmIrq(self, ch):
-        print("IRQ!")
+        #print("IRQ!")
         self.__event.set();
     
     def __WriteReg(self, reg, val):
@@ -192,9 +193,12 @@ class Rfm69:
                 self.__SetReg(RegDataModul, 0x03, value)
                 
             elif key == "SyncPattern":
-                conf = ((len(value) - 1) & 0x07) << 3
+                conf = 0
                 if (len(value)) > 0:
+                    conf = ((len(value) - 1) & 0x07) << 3
                     conf |= 1<<7
+                else:
+                    conf = 1<<6
                 self.__WriteReg(RegSyncConfig,  conf)
                 for i, d in enumerate(value):
                     self.__WriteReg(RegSyncValue1 + i, d)
@@ -216,6 +220,10 @@ class Rfm69:
                 
             elif key == "LnaGain":
                 self.__SetReg(RegLna, 0x03, value)
+
+            elif key == "RssiThresh":
+                th = -(value * 2)
+                self.__WriteReg(RegRssiThresh, th)
                 
             else:
                 print("Unrecognized option >>" + key + "<<")
@@ -234,10 +242,8 @@ class Rfm69:
             self.ReadReg(RegFifo)
             status = self.ReadReg(RegIrqFlags2)
             
-        self.__WriteReg(RegPayloadLength, 30)
-        self.__SetDioMapping(0, 0) # DIO0 -> PacketSent
-        self.__SetDioMapping(1, 2) # DIO1 -> FifoNotEmpty
-        
+        self.__WriteReg(RegPayloadLength, 0)
+        self.__SetDioMapping(0, 0) # DIO0 -> PacketSent        
         self.__WriteReg(RegOpMode, MODE_TX << 2) #TX Mode
         
         for i, d in enumerate(data):
@@ -248,50 +254,19 @@ class Rfm69:
                 while (status & 0x80) == 0x80:
                     status = self.ReadReg(RegIrqFlags2)    
 
-    
         #wait packet sent
-        status = self.ReadReg(RegIrqFlags2)
-        while (status & 0x08) == 0x00:
-           status = self.ReadReg(RegIrqFlags2)
-            #print ("s ", hex(status))
-
+        self.__event.wait()
+        self.__event.clear()
         self.__WriteReg(RegOpMode, MODE_STDBY << 2)
         self.__WaitMode()
-        return
                 
-        time.sleep(1)
-        
-        self.__WriteReg(RegOpMode, MODE_TX << 2) #TX Mode
-        
-        for d in [1, 2, 3, 4, 5]:
-            status = self.ReadReg(RegIrqFlags2)
-            #print "Status: ", hex(status)
-            #check FifoFull
-            #while (status & 0x80) == 0x80:
-              #  status = self.ReadReg(RegIrqFlags2)
-            #self.__WriteReg(RegFifo, d)
-            
-        #for x in range(16):
-        #   self.__WriteReg(RegFifo, 0x55)
-        
-        #self.__event.wait()
-        #self.__event.clear()
-        #check PacketSent
-        status = self.ReadReg(RegIrqFlags2)
-        while (status & 0x08) == 0x00:
-            #print "Status: ", hex(self.ReadReg(RegIrqFlags2))
-            status = self.ReadReg(RegIrqFlags2)
-        
-        self.__WriteReg(RegOpMode, 0) #idle mode
-        self.__WaitMode()
-        
     def ReceivePacket(self, length):
         self.__WriteReg(RegPayloadLength, length)
         
         self.__SetDioMapping(0, 1) #DIO0 -> PayloadReady
         self.__SetDioMapping(1, 3)
         self.__SetReg(RegOpMode, 7<<2, 4<<2) #RX mode
-        
+
         self.__event.wait()
         self.__event.clear()
 
@@ -301,4 +276,4 @@ class Rfm69:
         
         self.__WriteReg(RegOpMode, 0) #idle mode
         
-        return result
\ No newline at end of file
+        return result