578 lines
14 KiB
Python
578 lines
14 KiB
Python
import RPi.GPIO as GPIO
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import spidev
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import threading
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import time
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FXOSC = 32E6
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FSTEP = FXOSC / (1<<19)
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# Raspberry RFM Module connection
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# RaspyRFM single module
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# Connect to pins 17-26 on raspberry pi
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#--------------------------------#
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#Raspi|Raspi|Raspi|RFM69|RaspyRFM#
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#Name |GPIO |Pin |Name |PCB Pin #
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#--------------------------------#
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#3V3 | - | 17 |3.3V | 1 #
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# - | 24 | 18 |DIO1 | 2 # only when PCB jumper closed
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#MOSI | 10 | 19 |MOSI | 3 #
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#GND | - | 20 |GND | 4 #
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#MISO | 9 | 21 |MISO | 5 #
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# - | 25 | 22 |DIO0 | 6 #
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#SCKL | 11 | 23 |SCK | 7 #
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#CE0 | 8 | 24 |NSS | 8 #
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#CE1 | 7 | 26 |DIO2 | 10 # only when PCB jumper closed
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#--------------------------------#
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# RaspyRFM twin module with 10-pin connector
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# Connect to pins 17-26 on raspberry pi
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#---------------------------------#
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#Raspi|Raspi|Raspi|RFM69 |RaspyRFM#
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#Name |GPIO |Pin |Name |PCB Pin #
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#---------------------------------#
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#3V3 | - | 17 |3.3V | 1 #
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# - | 24 | 18 |DIO0_2| 2 #
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#MOSI | 10 | 19 |MOSI | 3 #
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#GND | - | 20 |GND | 4 #
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#MISO | 9 | 21 |MISO | 5 #
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# - | 25 | 22 |DIO0_1| 6 #
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#SCKL | 11 | 23 |SCK | 7 #
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#CE0 | 8 | 24 |NSS1 | 8 #
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#CE1 | 7 | 26 |NSS2 | 10 #
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#---------------------------------#
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# RaspyRFM twin module with 12-pin connector
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# Connect to pins 15-26 on raspberry pi
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#---------------------------------#
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#Raspi|Raspi|Raspi|RFM69 |RaspyRFM#
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#Name |GPIO |Pin |Name |PCB Pin #
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#---------------------------------#
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# - | 22 | 15 |DIO2_2| 1 #
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# - | 23 | 16 |DIO2_1| 2 #
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#3V3 | - | 17 |3.3V | 3 #
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# - | 24 | 18 |DIO0_2| 4 #
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#MOSI | 10 | 19 |MOSI | 5 #
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#GND | - | 20 |GND | 6 #
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#MISO | 9 | 21 |MISO | 7 #
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# - | 25 | 22 |DIO0_1| 8 #
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#SCKL | 11 | 23 |SCK | 9 #
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#CE0 | 8 | 24 |NSS1 | 10 #
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#CE1 | 7 | 26 |NSS2 | 12 #
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#---------------------------------#
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#RFM69 registers
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#common registers
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RegFifo = 0x00
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RegOpMode = 0x01
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RegDataModul = 0x02
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RegBitrateMsb = 0x03
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RegBitrateLsb = 0x04
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RegFdevMsb = 0x05
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RegFdevLsb = 0x06
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RegFrfMsb = 0x07
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RegFrfMid = 0x08
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RegFrfLsb = 0x09
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RegOsc1 = 0x0A
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RegAfcCtrl = 0x0B
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RegListen1 = 0x0D
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RegListen2 = 0x0E
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RegListen3 = 0x0F
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RegVersion = 0x10
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#TX registers
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RegPaLevel = 0x11
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RegPaRamp = 0x12
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RegOcp = 0x13
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#RX registers
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RegLna = 0x18
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RegRxBw = 0x19
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RegAfcBw = 0x1A
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RegOokPeak = 0x1B
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RegOokAvg = 0x1C
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RegOokFix = 0x1D
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RegAfcFei = 0x1E
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RegAfcMsb = 0x1F
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RegAfcLsb = 0x20
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RegFeiMsb = 0x21
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RegFeiLsb = 0x22
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RegRssiConfig = 0x23
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RegRssiValue = 0x24
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#IRQ & pin mapping registers
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RegDioMapping1 = 0x25
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RegDioMapping2 = 0x26
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RegIrqFlags1 = 0x27
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RegIrqFlags2 = 0x28
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RegRssiThresh = 0x29
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RegRxTimeout1 = 0x2A
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RegRxTimeout2 = 0x2B
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#packet engine registers
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RegPreambleMsb = 0x2C
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RegPreambleLsb = 0x2D
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RegSyncConfig = 0x2E
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RegSyncValue1 = 0x2F
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RegPacketConfig1 = 0x37
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RegPayloadLength = 0x38
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RegNodeAdrs = 0x39
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RegBroadcastAdrs = 0x3A
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RegAutoModes = 0x3B
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RegFifoThresh = 0x3C
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RegPacketConfig2 = 0x3D
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RegAesKey1 = 0x3E
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RegTemp1 = 0x4E
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RegTemp2 = 0x4F
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RegTestLna = 0x58
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RegTestDagc = 0x6F
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RegTestAfc = 0x71
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InterPacketRxDelay = 4 #Bitposition
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RestartRx = 2
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AutoRxRestartOn = 1
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AesOn = 0
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#Modulation type
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OOK = 1
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FSK = 0
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#DcFree
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DcFree_None = 0
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DcFree_Manchester = 1
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DcFree_Whitening = 2
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#RFM69 modes
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MODE_SLEEP = 0
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MODE_STDBY = 1
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MODE_FS = 2
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MODE_TX = 3
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MODE_RX = 4
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#DIO packet mode
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DIO0_PM_CRC = 0
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DIO0_PM_PAYLOAD = 1
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DIO0_PM_SYNC = 2
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DIO0_PM_RSSI = 3
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DIO0_PM_SENT = 0
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DIO0_PM_TXDONE = 1
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DIO0_PM_PLLLOCK = 3
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#Packet format
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PacketFormat_Fixed = 0
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PacketFormat_Variable = 1
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class Rfm69(threading.Thread):
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@staticmethod
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def test(cs, gpio_dio0):
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spi = spidev.SpiDev()
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spi.open(0, cs)
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spi.max_speed_hz = 5000
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#Testing presence of module
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err = False
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for i in range(8):
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spi.xfer2([(RegSyncValue1 + i) | 0x80, 0x55])
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test = spi.xfer2([(RegSyncValue1 + i), 0x00])[1]
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if test != 0x55:
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err = True
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break
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temp = spi.xfer2([(RegSyncValue1 + i) | 0x80, 0xAA])
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test = spi.xfer2([(RegSyncValue1 + i), 0x00])[1]
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if test != 0xAA:
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err = True
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break
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spi.close()
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return not err
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def __init__(self, cs = 0, gpio_int = 25):
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if not self.test(cs, gpio_int):
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print("ERROR! RFM69 not found")
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return
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self.__event = threading.Event()
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self.__spi = spidev.SpiDev()
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self.__spi.open(0, cs)
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self.__spi.max_speed_hz=int(5E6)
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self.__gpio_int = gpio_int
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self.__mutex = threading.Lock()
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self.__syncsize = 4
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self.__fifothresh = 32
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self.__packet_format = PacketFormat_Fixed
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print("RFM69 found on CS " + str(cs))
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GPIO.setmode(GPIO.BCM)
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GPIO.setup(gpio_int, GPIO.IN)
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GPIO.add_event_detect(gpio_int, GPIO.RISING, callback=self.__rfm_irq)
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self.__set_mode(MODE_STDBY)
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config = {}
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#SET DEFAULTS
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config[RegOpMode] = 0x04
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config[RegDataModul] = 0x00
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config[RegBitrateMsb] = 0x1A
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config[RegBitrateMsb + 1] = 0x0B
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config[RegFdevMsb] = 0x00
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config[RegFdevMsb + 1] = 0x52
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config[RegFrfMsb] = 0xE4
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config[RegFrfMsb + 1] = 0xC0
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config[RegFrfMsb + 2] = 0x00
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config[RegOsc1] = 0x41
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config[RegAfcCtrl] = 0x00
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config[0x0C] = 0x02 # reserved
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config[RegListen1] = 0x92
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config[RegListen2] = 0xF5
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config[RegListen3] = 0x20
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config[RegVersion] = 0x24
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config[RegPaLevel] = 0x9F
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config[RegPaRamp] = 0x09
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config[RegOcp] = 0x1A
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config[0x17] = 0x9B # reserved
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config[RegLna] = 0x88
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config[RegRxBw] = 0x55
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config[RegAfcBw] = 0x8B
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config[RegOokPeak] = 0x40
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config[RegOokAvg] = 0x80
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config[RegOokFix] = 0x06
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config[RegAfcFei] = 0x00
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config[RegAfcMsb] = 0x00
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config[RegAfcLsb] = 0x00
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config[RegFeiMsb] = 0x00
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config[RegFeiLsb] = 0x00
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config[RegRssiConfig] = 0x02
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config[RegDioMapping1] = 0x00
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config[RegDioMapping2] = 0x05
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config[RegIrqFlags1] = 0x80
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config[RegIrqFlags2] = 0x10
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config[RegRssiThresh] = 0xE4
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config[RegRxTimeout1] = 0x00
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config[RegRxTimeout2] = 0x00
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config[RegPreambleMsb] = 0x00
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config[RegPreambleLsb] = 0x00
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config[RegSyncConfig] = 0x98
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config[RegPacketConfig1] = 0x10
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config[RegPayloadLength] = 0x40
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config[RegNodeAdrs] = 0x00
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config[RegBroadcastAdrs] = 0x00
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config[RegAutoModes] = 0
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config[RegFifoThresh] = 0x8F
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config[RegPacketConfig2] = 0x02
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config[RegTemp1] = 0x01
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config[RegTemp2] = 0x00
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config[RegTestLna] = 0x1B
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config[RegTestDagc] = 0x30 #low beta 0
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config[RegTestAfc] = 0x00
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config[RegPacketConfig1] = 0x00 #Fixed length, CRC off, no adr
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for key in config:
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self.__write_reg(key, config[key])
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self.mode_standby()
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threading.Thread.__init__(self)
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print("Init complete.")
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def run(self):
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while True:
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time.sleep(0.5)
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def __rfm_irq(self, ch):
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self.__event.set()
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def __write_reg(self, reg, val):
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temp = self.__spi.xfer2([(reg & 0x7F) | 0x80, val & 0xFF])
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def __write_reg_word(self, reg, val):
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self.__write_reg(reg, (val >> 8) & 0xFF)
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self.__write_reg(reg + 1, val & 0xFF)
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def __set_reg(self, reg, mask, val):
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temp = self.read_reg(reg) & (~mask)
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temp |= val & mask
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self.__write_reg(reg, temp)
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def __set_dio_mapping(self, dio, mapping):
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if ((dio >= 0) and (dio <=3)):
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self.__set_reg(RegDioMapping1, 0xC0 >> (dio * 2), mapping << (6 - dio * 2))
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elif (dio == 5):
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self.__set_reg(RegDioMapping2, 0x03 << 4, mapping << 4)
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def __set_mode(self, mode):
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self.__write_reg(RegOpMode, mode << 2)
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self.__mode = mode
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while ((self.read_reg(RegIrqFlags1) & (1<<7)) == 0):
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pass
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def read_reg(self, reg):
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temp = self.__spi.xfer2([reg & 0x7F, 0x00])
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return temp[1]
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def read_fifo_burst(self, len):
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temp = self.__spi.xfer2([0x00] + [0x00] * len)
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return temp[1:]
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def write_fifo_burst(self, data):
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self.__spi.xfer2([0x80] + list(data))
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def read_reg_word(self, reg):
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temp = self.__spi.xfer2([reg & 0x7F, 0x00, 0x00])
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return (temp[1] << 8) | (temp[2])
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def read_rssi_value(self):
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return self.read_reg(RegRssiValue)
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def mode_standby(self):
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self.__set_mode(MODE_STDBY)
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def set_params(self, **params):
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self.__mutex.acquire()
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self.__event.set()
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for key in params:
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value = params[key]
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if key == "Freq":
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fword = int(round(value * 1E6 / FSTEP))
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self.__write_reg(RegFrfMsb, fword >> 16)
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self.__write_reg(RegFrfMid, fword >> 8)
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self.__write_reg(RegFrfLsb, fword)
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elif key == "TxPower":
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pwr = int(value + 18)
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self.__write_reg(RegPaLevel, 0x80 | (pwr & 0x1F))
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elif key == "Datarate":
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rate = int(round(FXOSC / (value * 1000)))
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self.__write_reg_word(RegBitrateMsb, rate)
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elif key == "Deviation":
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dev = int(round(value * 1000 / FSTEP))
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self.__write_reg_word(RegFdevMsb, dev)
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elif key == "ModulationType":
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self.__set_reg(RegDataModul, 0x18, value << 3)
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elif key == "ModulationShaping":
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self.__set_reg(RegDataModul, 0x03, value)
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elif key == "SyncPattern":
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conf = 0
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self.__syncsize = len(value)
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if (len(value)) > 0:
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conf = ((len(value) - 1) & 0x07) << 3
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conf |= 1<<7
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else:
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conf = 1<<6
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self.__write_reg(RegSyncConfig, conf)
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for i, d in enumerate(value):
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self.__write_reg(RegSyncValue1 + i, d)
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elif key == "AesKey":
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if (len(value)) > 0:
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self.__set_reg(RegPacketConfig2, 1<<0, 1<<0) #AES on
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else:
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self.__set_reg(RegPacketConfig2, 1<<0, 0<<0) #AES off
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for i, d in enumerate(value):
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self.__write_reg(RegAesKey1 + i, d)
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elif key == "Bandwidth":
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RxBw = FXOSC / value / 1000 / 4
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e = 0
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while (RxBw > 32) and (e < 7):
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e += 1
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RxBw /= 2
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RxBw = RxBw / 4 - 4
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RxBw = max(RxBw, 0)
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m = int(RxBw)
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self.__set_reg(RegRxBw, 0x1F, m<<3 | e)
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elif key == "AfcBandwidth":
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RxBw = FXOSC / value / 1000 / 4
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e = 0
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while (RxBw > 32) and (e < 7):
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e += 1
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RxBw /= 2
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RxBw = RxBw / 4 - 4
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RxBw = max(RxBw, 0)
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m = int(RxBw)
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self.__set_reg(RegAfcBw, 0x1F, m<<3 | e)
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elif key == "Preamble":
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self.__write_reg_word(RegPreambleMsb, value)
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elif key == "LnaGain":
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self.__set_reg(RegLna, 0x07, value)
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elif key == "RssiThresh":
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th = -(value * 2)
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self.__write_reg(RegRssiThresh, th)
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elif key == "Dagc":
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self.__write_reg(RegDagc, value)
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elif key == "AfcFei":
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self.__write_reg(RegAfcFei, value)
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elif key == "Callback":
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self.__callback = value
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elif key == "DcFree":
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self.__set_reg(RegPacketConfig1, 3<<5, value<<5)
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elif key == "OokThreshType":
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self.__set_reg(RegOokPeak, 3<<6, value<<6)
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elif key == "OokFixedThresh":
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self.__write_reg(RegOokFix, value)
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elif key == "OokPeakThreshDec":
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self.__set_reg(RegOokPeak, 7<<0, value)
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elif key == "PacketFormat":
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self.__set_reg(RegPacketConfig1, 1<<7, value<<7)
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self.__packet_format = value
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else:
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print("Unrecognized option >>" + key + "<<")
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self.mode_standby();
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self.__mutex.release()
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def __wait_int(self):
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self.__event.clear()
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if GPIO.input(self.__gpio_int):
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return
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while not self.__event.wait(0.5):
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if GPIO.input(self.__gpio_int):
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break
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def whiten_hope(self, data):
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lfsr = 0x3fe
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for i, d in enumerate(data):
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data[i] = data[i] ^ ((lfsr >> 2) & 0xFF)
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#roll LFSR
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for j in range(8):
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if ((lfsr >> 5) ^ lfsr) & 0x10 != 0:
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lfsr |= 1<<0
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lfsr <<= 1
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lfsr &= 0x3ff
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def whiten_ti(self, data):
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lfsr = 0x1ff
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for i, d in enumerate(data):
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data[i] = data[i] ^ (lfsr & 0xFF)
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for i in range(8):
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if ((lfsr >> 5) ^ lfsr) & 0x01 != 0:
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lfsr |= 1<<9
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lfsr >>= 1
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def send(self, data):
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self.__mutex.acquire()
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self.__event.set()
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self.mode_standby()
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#flush FIFO
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status = self.read_reg(RegIrqFlags2)
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while (status & 0x40 == 0x40):
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self.read_reg(RegFifo)
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status = self.read_reg(RegIrqFlags2)
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if self.__packet_format == PacketFormat_Variable:
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data.insert(0, len(data))
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else:
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self.__write_reg(RegPayloadLength, 0 if len(data) > 255 else len(data))
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self.__write_reg(RegFifoThresh, 0x80 | self.__fifothresh) #start TX with 1st byte in FIFO
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self.__set_dio_mapping(0, DIO0_PM_SENT) #DIO0 -> PacketSent
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self.__set_mode(MODE_TX)
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l = min(len(data), 64)
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while True:
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self.write_fifo_burst(data[:l])
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data = data[l:]
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if len(data) == 0:
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break
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while True:
|
|
status = self.read_reg(RegIrqFlags2)
|
|
if (status & (1<<5)) == 0: #below fifothresh
|
|
l = min(len(data), self.__fifothresh)
|
|
break
|
|
if (status & (1<<7)) == 0: #space for at least 1 bytearray
|
|
l = 1
|
|
break
|
|
|
|
self.__wait_int()
|
|
self.mode_standby()
|
|
self.__mutex.release()
|
|
|
|
def read_fifo_wait(self, length):
|
|
ret = []
|
|
while length > 0:
|
|
flags = self.read_reg(RegIrqFlags2)
|
|
if ((flags & (1<<5)) != 0) and (length >= 32): #FIFO level?
|
|
ret += self.read_fifo_burst(self.__fifothresh)
|
|
length -= self.__fifothresh
|
|
if (flags & (1<<6)) != 0: #FIFO not empty?
|
|
ret.append(self.read_reg(RegFifo))
|
|
length -= 1
|
|
return ret
|
|
|
|
def GetNoiseFloor(self):
|
|
self.__mutex.acquire()
|
|
#save values
|
|
rssithresh = self.read_reg(RegRssiThresh)
|
|
ookthresh = self.read_reg(RegOokFix)
|
|
sync = self.read_reg(RegSyncConfig)
|
|
|
|
self.__write_reg(RegRssiThresh, 240)
|
|
self.__write_reg(RegSyncConfig, 1<<6) #no sync, always fill FIFO
|
|
self.__write_reg(RegPayloadLength, 0) #unlimited length
|
|
self.__set_mode(MODE_RX)
|
|
thresh = 40
|
|
while True:
|
|
self.__write_reg(RegOokFix, thresh)
|
|
for i in range(150):
|
|
b = self.read_fifo_wait()
|
|
if b != 0:
|
|
thresh += 1
|
|
break;
|
|
if i == 149:
|
|
break;
|
|
|
|
#restore registers
|
|
self.__write_reg(RegRssiThresh, rssithresh)
|
|
self.__write_reg(RegOokFix, ookthresh)
|
|
self.__write_reg(RegSyncConfig, sync)
|
|
self.mode_standby()
|
|
self.__mutex.release()
|
|
return thresh
|
|
|
|
def __start_rx(self, length):
|
|
self.__mutex.acquire()
|
|
while True:
|
|
self.__write_reg(RegPayloadLength, length)
|
|
self.__write_reg(RegFifoThresh, self.__fifothresh)
|
|
if self.__syncsize > 0:
|
|
self.__set_dio_mapping(0, DIO0_PM_SYNC) #DIO0 -> SyncAddress
|
|
else:
|
|
self.__set_dio_mapping(0, DIO0_PM_RSSI) #DIO0 -> RSSI
|
|
self.__set_mode(MODE_RX)
|
|
self.__mutex.release()
|
|
self.__wait_int()
|
|
self.__mutex.acquire()
|
|
if self.__mode == MODE_RX:
|
|
break;
|
|
|
|
def start_receive(self, cb):
|
|
self.__start_rx(0)
|
|
cb(self)
|
|
self.mode_standby()
|
|
self.__mutex.release()
|
|
|
|
def receive(self, length):
|
|
self.__start_rx(length)
|
|
if self.__packet_format == PacketFormat_Variable:
|
|
length = self.read_fifo_wait(1)[0]
|
|
result = self.read_fifo_wait(length)
|
|
|
|
rssi = -self.read_reg(RegRssiValue) / 2
|
|
afc = self.read_reg(RegAfcMsb) << 8
|
|
afc = afc | self.read_reg(RegAfcLsb)
|
|
|
|
if afc >= 0x8000:
|
|
afc = afc - 0x10000
|
|
|
|
self.mode_standby()
|
|
self.__mutex.release()
|
|
return (result, rssi, afc)
|