Cleanup & improovments
This commit is contained in:
S. Seegel
parent
5681fd48e5
commit
e0a998ee52
3 changed files with 28 additions and 78 deletions
25
connair.py
25
connair.py
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@ -1,25 +0,0 @@
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#!/usr/bin/env python2.7
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import socket
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UDP_IP = "0.0.0.0"
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UDP_PORT = 49880
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HELLO_MESSAGE = "HCGW:VC:Seegel Systeme;MC:RaspyRFM;FW:1.00;IP:192.168.2.124;;"
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sock = socket.socket(socket.AF_INET, # Internet
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socket.SOCK_DGRAM) # UDP
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sock.bind((UDP_IP, UDP_PORT))
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while True:
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data, addr = sock.recvfrom(1024) # buffer size is 1024 bytes
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msg = str(data).split(":")
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print "received message:", msg, "from ", addr
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if msg[0] == "SEARCH HCGW":
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sock.sendto(HELLO_MESSAGE, addr)
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print "Hello message"
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if msg[0] == "TXP":
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cmd = msg[1].split(",")
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print "Command: ", cmd
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14
intertechno.py
Normal file → Executable file
14
intertechno.py
Normal file → Executable file
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@ -6,7 +6,8 @@ import sys
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import time
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if len(sys.argv) != 2:
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print "usage: intertechno <CODE>" #12-digit code 12 * ['0', '1', 'f']
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print "usage: intertechno <CODE>" #12-digit code 12 * ['0' | '1' | 'f']
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print "Example: intertechno 0FF0F0F00FF0"
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sys.exit(1)
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rfm = Rfm69()
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@ -15,13 +16,14 @@ rfm.SetParams(
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Datarate = 2.666666,
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TXPower = 13,
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ModulationType = rfm69.OOK,
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SyncPattern = [0x80, 0x00, 0x00, 0x00]
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SyncPattern = []
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)
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#Frame generation
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def MakeFrame(code, rep):
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data = [0x80, 0x00, 0x00, 0x00] #sync
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b = 0;
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data = []
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for c in code:
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if c == '0':
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data.append(0x88)
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@ -29,11 +31,9 @@ def MakeFrame(code, rep):
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data.append(0xEE)
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elif c == 'F' or c == 'f':
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data.append(0x8E)
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data += [0x80, 0x00, 0x00, 0x00] #sync
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result = []
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for i in range(rep):
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result += data
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return result
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return data * rep
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data = MakeFrame(sys.argv[1], 3)
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data = MakeFrame(sys.argv[1], 8)
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rfm.SendPacket(data)
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67
rfm69.py
67
rfm69.py
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@ -105,11 +105,7 @@ class Rfm69:
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GPIO.setmode(GPIO.BCM)
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GPIO.setup(gpio_int, GPIO.IN)
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GPIO.add_event_detect(gpio_int, GPIO.RISING, callback=self.__RfmIrq)
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self.__WriteReg(RegOpMode, MODE_STDBY << 2)
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self.__WaitMode()
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config = {}
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config[RegDataModul] = 0 #packet mode, modulation shaping, modulation
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config[RegPayloadLength] = 0
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@ -122,14 +118,19 @@ class Rfm69:
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config[RegTestDagc] = 0x30
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config[RegRssiThresh] = 0xE0
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config[RegFifoThresh] = 0x8F
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config[RegBitrateMsb] = 0x1A
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config[RegBitrateLsb] = 0x0B
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for key in config:
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self.__WriteReg(key, config[key])
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self.__WriteReg(RegOpMode, MODE_STDBY << 2)
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self.__WaitMode()
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print("INIT COMPLETE")
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def __RfmIrq(self, ch):
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print("IRQ!")
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#print("IRQ!")
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self.__event.set();
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def __WriteReg(self, reg, val):
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@ -192,9 +193,12 @@ class Rfm69:
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self.__SetReg(RegDataModul, 0x03, value)
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elif key == "SyncPattern":
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conf = ((len(value) - 1) & 0x07) << 3
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conf = 0
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if (len(value)) > 0:
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conf = ((len(value) - 1) & 0x07) << 3
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conf |= 1<<7
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else:
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conf = 1<<6
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self.__WriteReg(RegSyncConfig, conf)
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for i, d in enumerate(value):
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self.__WriteReg(RegSyncValue1 + i, d)
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@ -216,6 +220,10 @@ class Rfm69:
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elif key == "LnaGain":
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self.__SetReg(RegLna, 0x03, value)
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elif key == "RssiThresh":
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th = -(value * 2)
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self.__WriteReg(RegRssiThresh, th)
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else:
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print("Unrecognized option >>" + key + "<<")
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@ -234,10 +242,8 @@ class Rfm69:
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self.ReadReg(RegFifo)
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status = self.ReadReg(RegIrqFlags2)
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self.__WriteReg(RegPayloadLength, 30)
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self.__SetDioMapping(0, 0) # DIO0 -> PacketSent
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self.__SetDioMapping(1, 2) # DIO1 -> FifoNotEmpty
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self.__WriteReg(RegPayloadLength, 0)
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self.__SetDioMapping(0, 0) # DIO0 -> PacketSent
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self.__WriteReg(RegOpMode, MODE_TX << 2) #TX Mode
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for i, d in enumerate(data):
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@ -248,50 +254,19 @@ class Rfm69:
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while (status & 0x80) == 0x80:
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status = self.ReadReg(RegIrqFlags2)
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#wait packet sent
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status = self.ReadReg(RegIrqFlags2)
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while (status & 0x08) == 0x00:
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status = self.ReadReg(RegIrqFlags2)
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#print ("s ", hex(status))
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self.__event.wait()
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self.__event.clear()
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self.__WriteReg(RegOpMode, MODE_STDBY << 2)
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self.__WaitMode()
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return
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time.sleep(1)
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self.__WriteReg(RegOpMode, MODE_TX << 2) #TX Mode
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for d in [1, 2, 3, 4, 5]:
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status = self.ReadReg(RegIrqFlags2)
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#print "Status: ", hex(status)
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#check FifoFull
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#while (status & 0x80) == 0x80:
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# status = self.ReadReg(RegIrqFlags2)
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#self.__WriteReg(RegFifo, d)
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#for x in range(16):
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# self.__WriteReg(RegFifo, 0x55)
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#self.__event.wait()
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#self.__event.clear()
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#check PacketSent
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status = self.ReadReg(RegIrqFlags2)
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while (status & 0x08) == 0x00:
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#print "Status: ", hex(self.ReadReg(RegIrqFlags2))
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status = self.ReadReg(RegIrqFlags2)
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self.__WriteReg(RegOpMode, 0) #idle mode
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self.__WaitMode()
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def ReceivePacket(self, length):
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self.__WriteReg(RegPayloadLength, length)
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self.__SetDioMapping(0, 1) #DIO0 -> PayloadReady
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self.__SetDioMapping(1, 3)
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self.__SetReg(RegOpMode, 7<<2, 4<<2) #RX mode
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self.__event.wait()
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self.__event.clear()
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@ -301,4 +276,4 @@ class Rfm69:
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self.__WriteReg(RegOpMode, 0) #idle mode
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return result
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return result
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